A Semidigital Dual Delay-Locked Loop - Solid-State Circuits, IEEE Journal of
نویسندگان
چکیده
This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2 ) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8m CMOS technology is described. The prototype achieves an operating range of 80 kHz–400 MHz. At 250 MHz, its peakto-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV.
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